1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a metal oxide semiconductor (MOS) transistor having a fully silicided metal gate electrode.
2. Description of the Related Art
As electronic products employing semiconductor devices require light weight and small size, high integration density per unit area, low threshold voltage Vth, fast operating speed and low power consumption. Discrete devices such as MOS transistors are widely employed as switching devices for the semiconductor devices. To meet the requirement of the high integration, a gate of a transistor, source and drain junctions of the transistor, and interconnections should be reduced in size as much as possible within a possible range. In addition, the size of interconnections between the transistors should be also reduced.
However, the reduction of the transistor size has several associated difficulties. By way of example, the electrical resistance increases when the gate electrode is reduced. In this case, the transmission speed of an electrical signal applied to the gate electrode is delayed due to a resistance-capacitance (RC) delay time. In addition, a short channel effect occurs due to the reduction of the channel length.
To reduce the short channel effect, it is advantageous to form shallow source and drain junction depths and to form a thin gate insulating layer. However, the formation of the shallow source and drain junction depths causes an increase in sheet resistance of the source and drain. The increase of the sheet resistance in turn causes the current driving capability of the transistor to be degraded.
In the prior art of employing polysilicon for the gate electrode, the reduction of the gate electrode size further raises problems such as polysilicon depletion and boron penetration. In this case, the polysilicon depletion indicates a depletion region adjacent to the gate insulating layer, i.e., a lower region within the polysilicon gate electrode. The polysilicon depletion region serves as an additional capacitance which is serially connected to the capacitance of the gate insulating layer. As a result, the polysilicon depletion region causes the electrical equivalent thickness of the gate insulating layer to be increased. The increase of the electrical equivalent thickness means a decrease of an effective gate voltage. In the prior art of employing the thick gate insulating layer, since the thickness of the polysilicon depletion region is relatively very small compared to the effective thickness of the thick gate insulating layer, its effect may be negligible. However, when a thin gate insulating layer is used, the decrease in effective gate voltage due to the polysilicon depletion is raised as a serious problem.
The use of metal instead of polysilicon for the gate of the transistor has several advantages. For example, the metal material has a very high conductivity, and may avoid gate depletion and boron penetration. However, the metal gate causes the gate insulating layer to be degraded due to metal ions, and its work function is constant, which makes it difficult to adjust the threshold voltage Vth. For example, a semiconductor device such as a complementary MOS (CMOS) transistor has an N-MOS transistor region and a P-MOS transistor region within a single chip. Each threshold voltage of the N-MOS and P-MOS transistors should be adjusted to be different from each other. Consequently, a metal gate employed for the N-MOS transistor region should be different from that employed for the P-MOS transistor region, which makes the process very complicated.
To implement a high performance MOS transistor suitable for the highly integrated semiconductor device, research has been conducted on self-aligned silicide, i.e., salicide, technology. The salicide technology is a process of forming a metal silicide layer on the gate electrode and the source and drain regions to reduce electrical resistance of the gate electrode and the source and drain regions.
In this case, a metal gate may be formed when the gate electrode is fully transformed to a metal silicide, and the fully silicided metal may be implemented in N and P doped states even when the problematic N-MOS and P-MOS transistors are formed as mentioned above, which leads to a difference between work functions for the N-MOS and the P-MOS, so that the drawbacks of a metal gate may be overcome.
The metal silicide layer is also formed on the source and drain regions while the gate electrode is transformed to the silicide. When the thickness of the source/drain metal silicide layer is larger than the source and drain junction depth, leakage current occurs. Consequently, there exists a need for a technology capable of preventing the deep silicide layer from being formed in the source and drain regions while the gate electrode is fully transformed to silicide.
A method of forming a metal gate electrode using silicide is disclosed in U.S. Pat. No. 6,599,831B1 entitled “Metal gate electrode using silicidation and method of formation thereof” to Maszara et al.
FIG. 1 and FIG. 2 are cross-sectional views illustrating drawbacks to a method of fabricating a metal gate electrode using the silicide disclosed in U.S. Pat. No. 6,599,831B1.
Referring to FIG. 1, a gate electrode 86 and a capping layer 90 are sequentially stacked above a predetermined region of a semiconductor substrate 82. A gate insulating layer 84 is interposed between the gate electrode 86 and the semiconductor substrate 82. The gate electrode 86 is formed of doped polysilicon. First impurity ions are implanted into an active region of the semiconductor substrate 82 using the capping layer 90 as a mask to form lightly doped drain (LDD) regions 94 and 96. Spacers 104 and 106 surrounding sidewalls of the gate insulating layer 84, the gate electrode 86, and the capping layer 90 are then formed. Second impurity ions are implanted into the active region of the semiconductor substrate 82 using the capping layer 90 and the spacers 104 and 106 as masks to form source and drain regions 112 and 114.
Referring to FIG. 2, the capping layer 90 is selectively etched to expose the gate electrode 86. Next, a metal layer covering the gate electrode 86 and the source and drain regions 112 and 114 is formed, and a silicidation process is carried out.
However, to prevent the spacers 104 and 106 from being damaged while the capping layer 90 is etched, the capping layer 90 should be formed of a material having a high etch selectivity with respect to the spacers 104 and 106. Nevertheless, it is not easy to remove the capping layer 90. For example, when the capping layer 90 is an oxide layer, a trench isolation layer which is to be concurrently exposed may be damaged. Alternatively, when the capping layer 90 is a nitride layer, a trench liner which is to be concurrently exposed may be damaged.
In addition, when the capping layer 90 is not completely removed, it cannot be expected that the gate electrode 86 is fully transformed to silicide.